1. Field of the Invention
The invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a vertical transistor and a method for manufacturing the same.
2. Description of the Related Art
Regarding MOSFETs (Metal-Oxide-Semiconductor Field-Effect-Transistor), as the high density thereof has been developed, it is difficult to planarly lay out gates, sources and drains, which are components of the MOSFET. In DRAM (Dynamic Random Access Memory) having a minimum line pitch of about 90 nm or smaller, a three-dimensional layout is required. Here, the three-dimensional layout refers to a structure (hereinafter, referred to as vertical MOS transistor) in which a source and a drain (S/D) are provided above and below a pillar of a semiconductor (hereinafter, referred to as semiconductor pillar and when the semiconductor is silicon, it is referred to as silicon pillar) formed in a normal direction to a semiconductor substrate, a gate insulation film and a gate electrode (word line) are arranged on a surface of the silicon pillar and the respective components are overlapped in the normal direction of the semiconductor substrate.
For example, JP2008-288391A (hereinafter referred to as Reference 1) discloses a semiconductor device having a vertical MOS transistor of a structure shown in Drawing 1(a) of Reference 1. As shown, a vertical MOS transistor is disclosed in which a second diffusion layer (26) and a first diffusion layer (18) are arranged at the top and bottom of a first silicon pillar (15A) and a first gate insulation film (19A) and a first gate electrode (20A) are covered on a side surface of the first silicon pillar (15A). In this transistor, the first diffusion layer (18) and a wiring layer (30) are connected by a first contact plug (29a) and the second diffusion layer (26) and the wiring layer (30) are connected by a second contact plug (29b). Accordingly, charges supplied from the wiring layer (30) that is connected to a third contact plug (29c) reach the first gate electrode (20A) through a second gate electrode (20B), so that the transistor formed at the first pillar (15A) operates. As a result, the wiring layers (30) connected to the contact plug (29a) and the contact plug (29b) are made to conduct to each other. The reference numerals in the parentheses indicate those in the drawings of Reference 1, which is the same as the below. In order to stably operate the vertical MOS transistor, it is necessary to completely cover the conduction parts of the charges with an insulation film so as to prevent the charges from being leaked, so that a related method is needed.
In the vertical MOS transistor of Reference 1, the first gate electrode (20A) and the second diffusion layer (26) are insulated by a mask insulation film (14a) that is a silicon oxide film and a sidewall insulation film (25) that is a silicon nitride film. However, in a pre-process of forming the gate insulation film (19A), when wet etching is performed to remove an unnecessary oxide film on the substrate surface, a part of the mask insulation film (14a) is also removed, so that a cavity is formed. More specifically, a sidewall insulation film (16) shown in Drawing 6 of Reference 1 is formed on side surfaces of the first and second silicon pillars (15A), (15B) after an active area (13) is thermally oxidized and thus protected. Accordingly, a silicon oxide film (not shown) is interposed between the sidewall insulation film (16) and the first silicon pillar (15A) and abuts on the silicon oxide film (14a) that is a protective insulation film. From this state, in order to expose the side surface of the first silicon pillar (15A) so as to form the gate insulation film (19A), it is necessary to remove the sidewall insulation film (16) and the silicon oxide film that is a basis thereof by the wet etching, as shown in Drawing 9 of Reference 1. At this time, a part of the side surface of the silicon oxide film (14a) is also removed, so that a void is formed thereto.
The generation of the void is described with reference to FIG. 25. FIG. 25 is a process sectional view for illustrating the problems to be solved and is a partially enlarged view of the first silicon pillar (15A) of Reference 1, in which 100 is respectively added to the reference numerals of Reference 1. First, in FIG. 25(a), like Drawing 6 of Reference 1, a silicon oxide film 114a and a silicon nitride film 114b, which are mask insulation films, are stacked on a first silicon pillar 115A, and a silicon oxide film 116a and a silicon nitride film 116b are formed on a side surface of the first silicon pillar, as sidewall insulation films.
Next, like Drawing 9 of Reference 1, in order to remove the sidewall insulation film 16 and to thus expose the side surface of the first silicon pillar 115A, the silicon nitride film 116b and the silicon oxide film 116a are removed, as shown in FIG. 25(b). In order to speed up the transistor or to realize the low power consumption, the gate insulation film should be formed to be extremely thin. Accordingly, the silicon oxide film 116a should be securely removed so that it does not remain. Hence, a part of the side surface of the silicon oxide film 114a is removed, so that a cavity CV is formed.
Next, as shown in FIG. 25(c), the cavity CV remains even when an extremely thin gate insulation film 119A is formed. Then, a first gate electrode 120A is formed. However, the first gate electrode 120A is embedded in the cavity CV, too (refer to FIG. 25(d)). After that, when the silicon nitride film 114b above the first silicon pillar 115A is removed to form a sidewall 125 and the silicon oxide film 114a exposed into an opening is removed to form a through-hole 123, the first gate electrode 120A in the cavity CV can be exposed into the through-hole 123 (refer to FIG. 25(e)). As a result, a second diffusion layer formed in the through-hole 123 and the first gate electrode 120A can be short-circuited (refer to the broken line in FIG. 25(f)).